Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) including, for example, chips, thin film packages and printed circuit boards. ICs can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on the same semiconductor wafer.
For the device to be functional, the gate conductor of the pFETs and/or nFETs typically has minimal line edge roughness (LER) and line width roughness (LWR) so as to enable faster devices and ring oscillators. The term “ring oscillators” refers to a series of invertors the speed of which ultimately determines the clock speed of the integrated circuitry. In the case of polySi gate conductors, a minimal LER of about 3 nm and a minimal LWR of about 3 nm are obtained for conventional CMOS processing.
For current 65 nm CMOS devices, polySi gates of 100 nm thickness and 40 nm critical dimension (CD) are employed. For future technologies whereby continued device shrinking will be one methodology of achieving higher speed oscillators and circuits, it is essential that processing methodologies are developed to facilitate gates that have a CD of less than 40 nm with minimal LER and LWR.
In the prior art, the gate conductors are patterned utilizing the structure that is illustrated in FIG. 1. In particular, FIG. 1 shows a substrate 10, a gate dielectric 12 and a gate conductor 14. The gate conductor 14 has an ARC (antireflective coating) 16 thereon and a patterned photoresist 18 is located on the ARC 16. Patterning of the gate conductor is achieved by first trimming the ARC 16 and then utilizing an etching process which selectively removes the underlying gate conductor 14. The prior art structure illustrated in FIG. 1 suffers from the above-mentioned problems. In particular, this prior art structure does not adequately provide a means for achieving sub ground rule gate CDs.